Image reading apparatus

ABSTRACT

Delay circuit parts are disposed between a signal converting part and buffers. Since the capacities of delay elements provided respectively for the wiring of output wiring parts are different, time lag is generated respectively in the output timings of digital output signals outputted from the signal converting part relative to control clock signals. The output timings of the digital output signals shift so that the simultaneous switching of the digital output signals is prevented. Accordingly, EMI noise can be reduced without requiring the use of a special interface standard or the addition of shield members.

TECHNICAL FIELD

[0001] The present invention relates to an image reading apparatus.

BACKGROUND ART

[0002] In not only an image reading apparatus, but also an electroniccomputer and peripheral devices thereof (refer to the electroniccomputer and the peripheral devices thereof to as a “computer or thelike”, hereinafter), the generation of noise due to the influence of anelectromagnetic wave needs to be reduced. The computer or the like isrequested to perform various kinds of processes at high speed. In orderto perform the processes at high speed in the computer or the like, thefrequency of a clock signal for adjusting the operating timing ofelements or circuits respectively forming parts of the computer or thelike. At present, the frequency of the clock signal is widely set toseveral MHz to several GHz.

[0003] However, it has been known that, when the frequency of the clocksignal is raised, that is, when a high frequency is used for the clocksignal, the generation of an electromagnetic shield noise, what iscalled an EMI (Electro Magnetic Interference) noise increases. The EMInoise has a problem that the EMI noise is amplified when a switchingoperation (for instance, 0 to 1 or 1 to 0) is performed at the same timesynchronously with the clock signal, for instance, upon outputting thesignal.

[0004] To reduce the EMI noise, a special interface standard such as anECL or an SSTL has been hitherto used, cables of a transmission systemor the like have been coated with shield members, or EMI filters havebeen provided in all signal lines to reduce a noise level.

[0005] However, in the above-described case, the special interfacestandard is used or the shield members or the EMI filters need to beadded. Consequently, a cost is increased.

[0006] Further, even when the special interface standard is used or theshield members or the EMI filters are added as described above, theamplification of noise due to the simultaneous switching synchronouswith the clock signal is hardly reduced.

[0007] On the other hand, an image reading apparatus which has an imagepick-up unit such as a CCD (Charge Coupled Device) to form digital imagedata from an analog electric signal outputted from the image pick-upunit and output the digital image data has been known. From the imagepick-up unit of the image reading apparatus, the analog electric signalis outputted as described above. The analog electric signal is outputtedat a prescribed timing for each line. Therefore, the analog electricsignal outputted from the image pick-up unit needs to be specified to aprescribed output timing. Not only the image reading apparatus, but alsothe computer or the peripheral devices thereof use the clock signal of aprescribed frequency to specify the input and output timing of data or acalculating timing. The data is inputted and outputted or calculatedsynchronously with the clock signal.

[0008] In this image reading apparatus, a control signal synchronouswith the clock signal is used to specify the output timing of the analogelectric signal from the image pick-up unit.

[0009] In a usual image reading apparatus, for instance, two controlsignals are supplied to image pick-up unit to specify the output timingof an analog electric signal in accord with a cross-point at which thetwo control signals intersect. That is, the analog electric signal isoutputted from the image pick-up unit at the cross-point where the twocontrol signals intersect.

[0010] To allow the image pick-up unit to recognize the cross-point,voltage at the cross-point needs to be located within a prescribedrange.

[0011] However, the voltage at the cross-point is different for eachtype of the image pick-up unit, that is, every time the kind of theimage pick-up unit or a substrate changes. Each type of image pick-upunit has specific voltage characteristic of each image pick-up unit.Therefore, the voltage at the cross-point of the control signals needsto be set to the specific voltage for each of the image pick-up unit.When the voltage at the cross-point is not the specific voltage, theanalog electric signal is not outputted from the image pick-up unit.Accordingly, each image pick-up unit needs to be strictly adjusted sothat the voltage at the cross-point becomes the specific voltage.

[0012] Thus, a resistance element or a capacitor element or the like hasbeen hitherto disposed in a control signal circuit part for supplying acontrol signal to image pick-up unit. Thus, a resistance value or acapacity thereof has been adjusted to adjust the waveform of the controlsignal and voltage at a cross-point.

[0013] However, since the specific voltage is different for each imagepick-up unit, the resistance value or the capacity of the resistanceelement or the capacitor element needs to be adjusted for each imagepick-up unit. Therefore, after the image pick-up unit is disposed on,for instance, a substrate, an externally attached adjusting circuitincluding a resistance element or a capacitor element needs to beprovided to adjust the waveform of a control signal in accordance withthe specific voltage of the image pick-up unit. As a result, theadjustment of the voltage at the cross-point disadvantageously becomescomplicated.

[0014] Accordingly, it is an object of the present invention to providean image reading apparatus in which EMI noise is reduced and theamplification of noise due to a simultaneous switching operation isreduced without requiring the use of a special interface standard or theaddition of a shield member.

[0015] Further, it is another object of the present invention to providean image reading apparatus in which voltage at a cross-point is easilyadjusted without requiring the adjustment of a waveform and anexternally attached circuit.

DISCLOSURE OF THE INVENTION

[0016] An image reading apparatus according to the first invention hasoutput timing changing unit in an output side of an output signalgenerating unit. The output timing changing unit changes the outputtiming of each digital output signal forming a plurality of digitaloutput signals outputted from the output signal generating unit for eachdigital output signal. That is, the output timing of the digital outputsignal outputted from the output signal generating unit is changed foreach of digital output signals corresponding to the number of outputbits. Therefore, the waveform of the digital output signal is differentfor each digital output signal, so that the simultaneous switching canbe prevented. Since the waveform of the digital output signal isdifferent for each digital output signal, the current peaks of theoutputted signals are dispersed to lower the peak of noise generatedfrom cables of a transmission system. As a result, EMI noise is reducedto improve an S/N ratio. Accordingly, the EMI noise can be reducedwithout requiring the use of a special interface standard or theaddition of shield members and the amplification of noise due to thesimultaneous switching can be reduced.

[0017] Further, the output timing changing unit shifts the output timingin view of time for each digital output signal. Since a clock signal isessentially used to synchronize the operations of a computer such as theimage reading apparatus or the like, the digital output signalsspecified by the clock signal are also desirably outputted synchronouslywith the clock signal. However, as described above, the digital outputsignals are switched at the same time synchronously with the clocksignal to amplify the EMI noise. Thus, the output timing changing unitshifts the output timing so as not to avoid the synchronization of theclock signal with the digital output signal to prevent the simultaneousswitching of the digital output signals. For instance, in the clocksignal of a prescribed frequency, a reference clock signal is used sothat a phase can be adjusted during one cycle of the clock signal. Asdescribed above, the output timing of the digital output signal isshifted so that the simultaneous switching of the digital output signalscan be prevented and the amplification of the EMI noise can beprevented.

[0018] Further, delay circuit parts are respectively disposed in outputwiring parts. The delay circuit parts respectively delay the outputtimings of the digital output signals in view of time. For instance,when the output signal generating unit is disposed on a substrate, thedelay circuit parts are merely disposed on the substrate. Accordingly,the delay circuit parts are easily formed.

[0019] Further, the delay circuit parts are set so that an amount ofdelay of the output timing of the digital output signal is different foreach of the delay circuit parts. Accordingly, the output timing of thedigital output signal is shifted for each digital output signal so thatthe amplification of the EMI noise due to the simultaneous switching canbe reduced and noise generated due to the dispersion of current peakscan be reduced.

[0020] Further, the output timing changing unit changes a frequency foreach digital output signal. In other words, the output timing changingunit changes a length of one cycle of the digital output signal, thatis, a wavelength. When the frequency of the digital output signal ischanged, the output timing of the digital output signal is shifted foreach digital output signal. As a result, the simultaneous switching ofthe digital output signals can be prevented and the EMI noise can beprevented from being amplified.

[0021] Further, the output timing changing unit includes a plurality ofdelay circuit parts respectively disposed in the output wiring parts anda selector for selecting an arbitrary delay circuit part from among theplural delay circuit parts. An amount of delay is set so as to bedifferent for each of the delay circuit parts. Then, when the selectorselects one delay circuit part, the amount of delay is different foreach output wiring part. Therefore, the output timing of the digitaloutput signal can be changed at random for each of the output wiringparts. Further, the output timing of the digital output signal ischanged at random for each output wiring part, so that not only theoutput timing, but also the frequency can be changed. Therefore, theamplification of the EMI noise due to the simultaneous switching and thenoise generated due to the dispersion of current peaks can be reduced.

[0022] An image reading apparatus according to the second inventionincludes cross-point adjusting unit. The cross-point adjusting unitrespectively controls the amount of delay of a plurality of controlsignals in view of time for each of the control signals to adjustvoltage at a cross-point by adjusting the amount of delay of eachcontrol signal. Since the cross-point adjusting unit is provided, anexternally attached adjusting circuit does not need to be provided afterimage pick-up unit is provided. Accordingly, the amount of delay of thecontrol signal can be adjusted for each image pick-up unit by thecross-point adjusting unit. The capacity of an element of an externallyattached circuit does not need to be adjusted, and accordingly, specificvoltage and the voltage at the cross-point are easily adjusted.

[0023] Further, the amount of delay of the plural control signals isadjusted for each control signal. That is, the voltage at thecross-point is adjusted by adjusting the amount of delay. Therefore, thedeterioration of the control signal can be prevented and the incompleteoperation of the image pick-up unit can be prevented.

[0024] Further, the image reading apparatus includes recording unit. Therecording unit can record the amount of delay of a plurality of controlsignals corresponding to the specific voltage in view of time.Accordingly, when the amount of delay of the control signal is recordedin the recording unit, for instance upon shipment, the voltage at thecross-point can be adjusted at any time on the basis of the recordedamount of delay.

[0025] Further, the cross-point adjusting unit includes a plurality ofdelay circuit parts and a selector. The delay circuit parts respectivelychange an amount of delay in view of time for each control signal of theplural control signals supplied to the image pick-up unit. The pluraldelay circuit parts are provided to finely set the amount of delay foreach control signal. The selector selects a specific delay circuit partwith an amount of delay suitable for adjusting the voltage at the crosspoint from among the plural delay circuit parts. Thus, the amount ofdelay of the control signal can be finely controlled and the voltage atthe cross-point can be precisely controlled.

[0026] Further, the selector selects the specific delay circuit part onthe basis of the amount of delay recorded on the recording unit.Accordingly, the cross-point adjusting unit can always control thevoltage at the cross-point to a prescribed value.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is a schematic view showing a signal output part of animage reading apparatus according to a first embodiment of the presentinvention.

[0028]FIG. 2 is a block diagram showing the image reading apparatusaccording to the first embodiment of the present invention.

[0029]FIG. 3 is a schematic view showing a timing chart of a case inwhich output timing changing unit is not provided for comparison.

[0030]FIG. 4 is a schematic view showing a timing chart of the imagereading apparatus according to the first embodiment of the presentinvention.

[0031]FIG. 5 is a schematic view showing a cross-point adjusting part ofthe image reading apparatus according to the first embodiment of thepresent invention.

[0032]FIG. 6 is a schematic view showing a timing chart of a controlsignal outputted from the cross-point adjusting part of the imagereading apparatus according to the first embodiment of the presentinvention.

[0033]FIG. 7 is a schematic view showing a signal output part of animage reading apparatus according to a second embodiment of the presentinvention.

[0034]FIG. 8 is a schematic view showing a timing chart of the imagereading apparatus according to the second embodiment of the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0035] Now, a plurality of embodiments showing modes for carrying outthe present invention will be described in detail by referring to thedrawings.

FIRST EMBODIMENT

[0036] An image reading apparatus according to a first embodiment isshown in FIG. 2. The image reading apparatus according to the firstembodiment is a flat bed type image reading apparatus.

[0037] As shown in FIG. 2, the image reading apparatus 1 includes acarriage 20 and a main control part 30 in a box shaped main body 10. Adata holder 11 is arranged on an upper part of the main body 10. A copyto be read is mounted on the part of the data holder 11 opposite to thecarriage side. The carriage 20 disposed in the main body 10 canreciprocate in a sub-scanning direction in parallel with the data holder11 by a driving device not shown in the drawing.

[0038] On the carriage 20, a light source 21, a converging lens 22, aline sensor 23 as image pick-up unit, an A/D converting part 24, asignal output part 40 as output signal generating unit and a carriagecontrol part 26 are mounted.

[0039] The converging lens 22 converges light from data on the linesensor 23. As the line sensor 23, a charge storage type optical sensorsuch as a CCD in which a plurality of pixels are linearly arranged in amain scanning direction perpendicular to the moving direction of thecarriage 20 is employed.

[0040] The light source 21 is provided perpendicularly to the movingdirection of the carriage 20. A fluorescent lamp or the like is used.Light applied from the light source 21 is reflected on the surface of areflecting copy such as a sheet and incident on the line sensor 23.

[0041] The A/D converting part 24 converts an analog electric signaloutputted from the line sensor 23 to a digital electric signal. Thesignal output part 40 generates and outputs a plurality of digitaloutput signals corresponding to the number of bits from the digitalelectric signal outputted from the A/D converting part 24. In the outputside of the signal output part 40, output timing changing unit 45 isprovided.

[0042] The carriage control part 26 controls respective components ofthe carriage 20 in accordance with an instruction from the main controlpart 30. In the carriage control part 26, a clock generating part 261 isprovided as clock signal supply unit.

[0043] The main control part 30 includes a microcomputer 31, an imageprocessing ASIC (Application Specific IC) 32 and an interface 33. Themicrocomputer 31 includes a CPU (Central Processing Unit), a RAM (RandomAccess Memory) and a ROM (Read Only Memory) or the like which are notshown in the drawing to control the respective parts of the imagereading apparatus 1 via the image processing ASIC 32.

[0044] The image processing ASIC 32 includes a clock generating circuit321, and a shading correction part, a gamma correction part and othercorrection parts that are not shown in the drawing. The clock generatingcircuit 321 supplies a basic clock signal to each part of the imagereading apparatus 1. The image processing ASIC 32 carries out variouskinds of processes to the digital output signal outputted from thesignal output part 40 of the carriage 20 to form digital image data.

[0045] The shading correction part carries out a shading correction tothe digital output signal outputted from the signal output part 40. Forexample, unevenness in the sensitivity for each pixel of the line sensor23 and unevenness in the quantity of light of the light source 21 in themain scanning direction are corrected by using data obtained by readinga white reference before a reading operation is started. The gammacorrection part carries out a gamma correction by a prescribed gammafunction to convert a shading corrected digital output signal to digitalimage data. Other correction part carries out various conversions suchas a color correction, an edge emphasis and enlargement/reduction ofarea, etc.

[0046] The digital image data prepared in the image processing ASIC 321is outputted to an image processor such as a personal computer connectedto an external part from the interface 33.

[0047] In the clock generating circuit 321, the basic clock signal of alow frequency is generated. The generated basic clock signal is suppliedto the clock generating part 261 of the carriage control part 26. In theclock generating part 261, the basic clock signal of the low frequencygenerated in the clock generating circuit 321 is sequentially multipliedto generate a control clock signal. The control clock signal generatedin the clock generating part 261 is supplied to the line sensor 23, theA/D converting part 24 and the signal output part 40.

[0048] From the clock generating circuit 321 of the main control part30, the basic clock signal of the low frequency, for instance, about 6Hz is supplied. The basic clock signal supplied to the carriage controlpart 26 is multiplied by 16 in the clock generating part 261 andsupplied to the line sensor 23, the A/D converting part 24 and thesignal output part 40 as the control clock signal of 96 MHz. The linesensor 23, the A/D converting part 24 and the signal output part 40operate synchronously with the supplied control clock signal.

[0049] An electric charge stored synchronously with the control clocksignal is outputted as an analog electric signal from the line sensor23. In the A/D converting part 24, a digital electric signal isgenerated from the analog electric signal. The generated digitalelectric signal is outputted as a digital output signal synchronouslywith the control clock signal from the signal output part 40.

[0050] The clock generating part 261 of the carriage control part 26sequentially multiplies the basic clock signal of the low frequencygenerated in the clock generating circuit 321 as clock signal generatingunit disposed in the main control part 30 to form an operating clocksignal of a high frequency. The operating clock signal generated in theclock generating part 261 is supplied to the line sensor 23, the A/Dconverting part 24, the signal output part 40 and a cross-pointadjusting part 50.

[0051] The cross-point adjusting part 50 generates a control signal fromthe operating clock signal generated in the clock generating part 261 ofthe carriage control part 26. The cross-point adjusting part 50 adjuststhe amount of delay of the control signal and the cross-point of thecontrol signal in accordance with an instruction from the main controlpart 30.

[0052] Now, the signal output part will be described in detail.

[0053] The signal output part 40 generates the digital output signalscorresponding to the number of output bits from the digital electricsignal outputted from the A/D converting part 24. In this embodiment, acase in which the number of output bits is 4 bits is described.

[0054] As shown in FIG. 1, the signal output part 40 has data wiringparts 41, a signal converting part 42 and an output wiring part 43. Thedata wiring parts 41 are electric wiring for connecting the A/Dconverting part 24 to the signal converting part 42. The signalconverting part 42 converts the digital electric signal inputted fromthe data wiring parts 41 to the digital output signals corresponding tothe number of output bits. The output wiring part 43 is electric wiringfor outputting the digital output signals converted in the signalconverting part 42.

[0055] The data wiring parts 41, the signal converting part 42 and theoutput wiring part 43 are formed on a single substrate or a single chipto constitute a signal output ASIC.

[0056] The output wiring part 43 has four wiring 430, 431, 432 and 433corresponding to the four bits as the number of output bits. Outputbuffers 44 are respectively provided in the four wiring 430 to 433. Theoutput buffers 44 improve the driving performance of the output signals.Between the signal converting part 42 and the output buffers 44, anoutput timing changing unit 45 for changing the output timing of theoutput signal is provided. The output timing changing unit 45 includesdelay circuit parts 451, 452 and 453 disposed respectively in the outputwiring part 43 between the signal converting part 42 and the outputbuffers 44. The delay circuit parts 451 to 453 are composed of delayelements, for instance, capacitors. The capacities of the delay elementsare different respectively for the delay circuit parts.

[0057] The control clock signal is supplied to the signal convertingpart 42 from the clock generating part 261. From the signal convertingpart 42, the digital output signals corresponding to the number ofoutput bits are outputted synchronously with the control clock signal.For instance, when an output has 2 bits, a signal D0 and a signal D1outputted from the wiring 430 and the wiring 431 of the output wiringpart 43 are “1”, and a signal D2 and a signal D3 outputted from thewiring 432 and the wiring 433 are “0”. The digital output signals fromthe signal converting part 42 are outputted to the image processing ASIC32 of the main control part 30 via the output wiring part 43.

[0058] Now, an operation of the signal output part 40 will be describedbelow.

[0059] As described above, the digital output signals are outputtedsynchronously with the control clock signal from the signal convertingpart 42. Therefore, for instance, when the output timing changing unit45 is not provided, the signals D0 to D3 outputted via the output wiringpart 43 are switched synchronously with the control clock signal asshown in FIG. 3. That is, as shown in FIG. 3, the signals simultaneouslychange from 0 to 1 or from 1 to 0 in an output timing tn (n is anarbitrary integer). Accordingly, as shown in a timing t0, all thesignals may be switched from “0” to “1” synchronously with the controlclock signal. When a plurality of signals are switched in the samemanner synchronously with the control clock signal as described above,EMI noise is amplified.

[0060] In this embodiment, the output timing changing unit 45 isprovided between the signal converting part 42 and the output buffers44. Thus, the output signals outputted from the signal converting part42 have time lag respectively generated in switching in the signals D0to D3 outputted from the wiring 430 to 433 depending on the capacitiesof the delay elements of the delay circuit parts 451 to 453. As shown inFIG. 1, when the delay element is not provided in the wiring 430 and thecapacities of the delay elements are increased in order in the wiring431, 432 and 433, signals D0 to D4 outputted from the signal convertingpart 42 have respectively time lag generated as shown in FIG. 4.

[0061] Therefore, even when the signals D0 to D4 are outputtedsynchronously with the clock signal, the switching from “0” to “1” orthe switching from “!” to “0” is not generated at the same time. As aresult, the amplification of the EMI noise is reduced.

[0062] The signals D0 to D4 having the time lag generated by the outputtiming changing unit 45 are inputted to the image processing ASIC 32 andthen the time lag is adjusted synchronously with the basic clock signaloutputted from the clock generating circuit 321.

[0063] Now, the cross-point adjusting part 50 will be described indetail.

[0064] The cross-point adjusting part 50 is connected to the line sensor23 as shown in FIG. 5. The cross-point adjusting part 50 includescontrol signal generating parts 51 for generating control signals, delaycircuit parts 52, selectors 53 and control signal supply wiring parts54. In the control signal generating part 51, the control signal isgenerated synchronously with the operating clock signal supplied fromthe clock generating part 261. In this embodiment, two control signalsare generated synchronously with the operating clock signal.

[0065] The delay circuit parts 52 are respectively provided in the linesensor 23 side of the control signal generating parts 51 to change theamounts of delay of the control signals outputted from the controlsignal generating parts 51. Each delay circuit part 52 includes fourdelay circuits 520, 521, 522 and 523 having delay elements respectivelyhaving different amounts of delay. The amount of delay means a time lagof the control signals and its unit is “sec”. As the delay element, forinstance, a capacitor element or a resistance element is used. In thisembodiment, the amount of delay of the delay circuit 520 is set to 0nsec. The amount of delay of the delay circuit 521 is set to 1 nsec. Theamount of the delay circuit 522 is set to 3 nsec and the amount of delayof the delay circuit 523 is set to 8 nsec. These amounts of delay arecombined together so that the time lags of 0, 1, 2, 3, 5, 7 and 8 nsecscan be set to the control signals outputted from the two control signalgenerating parts 51. The selectors 53 are provided in the line sensor 23side of the delay circuit parts 52 to select specific delay circuitsfrom the delay circuits 520 to 523 forming the delay circuit parts 52 inaccordance with an instruction of the microcomputer 31 of the maincontrol part 30. When the selectors 53 select the specific delaycircuits, any of the above-described amounts of delay is set. Thecontrol signal supply wiring parts 54 supply the control signalsgenerated in the control signal generating parts 51 to the line sensor23.

[0066] Now, an operation of the cross-point adjusting part 50 will bedescribed below.

[0067] The output timing of the analog electric signal outputted fromthe line sensor 23 is controlled by the control signals. That is, asshown in FIG. 6, a cross-point P at which the control signals Φ1 and Φ2outputted from the two control signal generating parts 51 cross isspecified as the output timing of the analog electric signal from theline sensor 23. In other words, the analog electric signal is outputtedfrom the line sensor 23 every time the two control signals Φ1 and Φ2cross.

[0068] The line sensor 23 is set so that the line sensor outputs theanalog electric signal when voltage in the intersection of these controlsignals Φ1 and Φ2 is located within a prescribed range of, for instance,2.0 V to 3.0 V. The voltage of the cross-point P and the range of thevoltage are different respectively for various types of line sensors 23by setting in design and determined as specific cross-pointsrespectively for the line sensors 23. Accordingly, the amounts of delayof the control signals D1 and D2 need to be adjusted so that the voltageat the cross-point P is located within a range determined for each ofthe line sensors 23.

[0069] As shown in FIG. 6, when the specific voltage is set to 2.0 V to3.0 V, the voltage of the cross-point P is not located within the rangeof the specific voltage depending on the waveforms of the controlsignals Φ1 and Φ2 as shown in FIG. 6(A). The deformation of thewaveforms of the control signals Φ1 and Φ2 is generated from variouskinds of factors such as the capacities of pixels forming the linesensor 23 or the difference of electric resistance for each wiring ofthe control signal supply wiring parts 54 connected to the line sensor23.

[0070] Thus, in this embodiment, as shown in FIG. 6(B), a time lag isgenerated in the control signal Φ2, that is, the control signal Φ2 isdelayed to adjust the voltage at the cross-point P to 2.0 V to 3.0 V asthe specific voltage.

[0071] The amounts of delay of the control signals Φ1 and Φ2 are set foreach type of line sensors 23 and previously recorded in the ROM 342 of arecording part 34. Upon using the image reading apparatus 1, themicrocomputer 31 controls the selectors 53 on the basis of the amountsof delay recorded in the ROM 342 to select the delay circuits so as tohave prescribed amounts of delay. Therefore, in the two control signalsΦ1 and Φ2 outputted from the control signal generating parts 51, thevoltage in the cross-point P is adjusted to the specific voltage of theline sensor 23. The amounts of delay are controlled for each of outputtimings of the control signals.

[0072] For instance, in producing the image reading apparatus 1, when acarriage base 4 is previously produced, and then, the line sensor 23 ismounted on the carriage base 4, the amounts of delay of the controlsignals Φ1 and Φ2 are determined so as to correspond to the specificvoltage different for each of the line sensors 23 and the amounts ofdelay are stored in the ROM 342. Then, the microcomputer 31 controls theselectors 53 on the basis of the amounts of delay stored in the ROM 342to control the amounts of delay of the control signals 41 and Φ2.

[0073] Now, an operation of the above-described image reading apparatus1 will be described below.

[0074] A user mounts data desired to be read on the data holder 11 andinstructs the image reading apparatus 1 to start to read the data via adriver program for controlling the image reading apparatus 1 such as aTWAIN activated by a personal computer.

[0075] When the user instructs to start to read the data, themicrocomputer 31 turns on the light source 21. Then, the carriage 20 ismoved in the sub-scanning direction at prescribed speed in accordancewith the instruction of the microcomputer 31. Light reflected on thedata is made incident on the line sensor 23. The incident light isconverted into an electric charge and the electric charge is stored. Thestored electric charge is transferred to a shift register (not shown) ofthe line sensor 23 synchronously with the control clock signal and theanalog electric signal of one line is outputted from the line sensor 23.The analog electric signal outputted from the line sensor 23 isoutputted to the image processing ASIC 32 via the A/D converting part 24and the signal output part 40. The digital image data prepared in theimage processing ASIC 32 is outputted to the personal computer via theinterface 33.

[0076] While the carriage 20 is moved in the sub-scanning direction atprescribed speed, the above-described processes are repeated to read thedata.

[0077] As described above, in the image reading apparatus 1 according tothe first embodiment of the present invention, the digital outputsignals outputted from the signal converting part 42 of the signaloutput part 40 are outputted with time lag by the delay circuit parts451 to 453 of the output timing changing unit 45. Accordingly, the EMInoise due to the simultaneous switching can be reduced.

[0078] Further, in the first embodiment, the delay circuit parts 451 to453 are disposed on a substrate on which the signal converting part 42is formed near the output wiring part 43 of the signal converting part42 or on the same substrate as the chip or on the chip. Therefore, thedelay circuit parts 451 to 453 can be disposed simultaneously with theformation of the signal converting part 42, so that manufacturing stepsare not increased or a wiring structure is not complicated. Further,since the special interface or the shield members or the like forshielding the EMI noise are not necessary, the manufacture cost is notincreased.

[0079] Further, in the image reading apparatus 1 according to the firstembodiment of the present invention, a plurality delay circuits 520 to523 are provided in the cross-point adjusting part 50. Then, thespecific delay circuits are selected from these plural delay circuits520 to 523 so that the amounts of delay of the control signals Φ1 and Φ2can be accurately adjusted. Accordingly, voltage at the cross-point Pcan be easily adjusted within a range of the specific voltage. As aresult, even when the specific voltage of the line sensor 23 isdifferent for each image reading apparatus 1, an external circuit foradjusting the voltage at the cross-point P is not required and thevoltage at the cross-point P can be easily and accurately adjusted.

[0080] Further, the amounts of delay are recorded in the ROM 342 of therecording part 34. Thus, the amounts of delay are set, for instance,upon shipment, so that the amounts of delay of the control signals Φ1and Φ2 can be adjusted at any time during the use of the image readingapparatus 1.

SECOND EMBODIMENT

[0081] A second embodiment of the present invention is shown in FIG. 7.Components substantially the same as those of the first embodiment aredesignated by the same reference numerals and the explanation thereofwill be omitted.

[0082] In the second embodiment, the structure of an output timingchanging unit is different from that of the first embodiment. In thesecond embodiment, the output timing changing unit includes a randomenable signal output part 61 and a select signal output part 62.

[0083] The random enable signal output part 61 generates a signal forchanging the output timing itself of a digital output signal outputtedfrom a signal converting part 42 and outputs the signal to the signalconverting part 42.

[0084] In the signal converting part 42, a delay circuit part 63 isprovided. The delay circuit part 63 is respectively connected to thesignal converting part 42. The delay circuit part 63 includes aplurality of delay circuits 630 to 633 respectively connected to thesignal converting part 42. The amounts of delay of circuits respectivelyforming the delay circuits 630 to 633 are different. For example, theamount of delay of the delay circuit 630 is 0. The amount of delay ofthe delay circuit 630 is respectively different from those of the delaycircuit 631, the delay circuit 632 and the delay circuit 633. In theoutput side of the delay circuits 630 to 633, selectors 634 aredisposed. The selectors 634 are connected to the select signal outputpart 62. The select signal output part 62 outputs a select signal toeach selector 634. Then, the selector 634 selects any of the delaycircuits 630 to 633 for each of output timings of the digital outputsignals outputted from the signal converting part 42 on the basis of theoutputted select signal. That is, since the delay circuit selected foreach output signal of the digital output signal is different dependingon the select signal outputted from the select signal output part 62,the output timings of the digital output signals outputted from thesignal converting part 42 are changed by a prescribed amount.

[0085] In a random enable signal or the select signal respectivelyoutputted from the random enable signal output part 61 and the selectsignal output part 62, a change point of the digital output signal ischanged for each clock in a specific area by using a clock signal of acycle faster than that of the clock signal generated in the clockgenerating circuit 321, for instance, a clock signal of 16 times asshown in FIG. 8. That is, the change point of the digital output signalis changed by using the control clock signal having a cycle faster thanthat of a basic clock signal in which data is sampled in the imageprocessing ASIC 32.

[0086] Now, an operation of the output timing changing unit according tothe second embodiment will be described below.

[0087] As described above, the output timing of the digital outputsignal outputted from the signal converting part 42 synchronously withthe control clock signal changes depending on the output timing itselfof the signal converting part 42 and the amounts of delay of the delaycircuit part 63 connected to the signal converting part 42.Specifically, the output timing of the digital output signal outputtedfrom the signal converting part 42 changes in accordance with the randomenable signal outputted from the random enable signal output part 61.Further, since the selector 634 selects any of the delay circuits 630 to633 by the select signal outputted from the select signal output part62, the output timing of and the mount of delay of the digital outputsignal finely change for each clock signal. The random enable signal andthe select signal are outputted from the random enable signal outputpart 61 or the select signal output part 62 synchronously with thecontrol clock signal.

[0088] As described above, the output timing and the amount of delay ofthe digital output signal are changed, so that the output timing of thedigital output signal changes at random as shown in FIG. 8. Usually, asshown in FIG. 8, digital output signals have been respectively outputtedat the same time from the signal converting parts 42 synchronously withthe basic clock and the control clock. As compared therewith, in thisembodiment, the output timing can be changed.

[0089] Frequency changed by the output timing changing unit is inputtedto the image processing ASIC 32, and then, the frequency is correctedsynchronously with the basic clock signal outputted from the clockgenerating circuit 321 and adjusted to a prescribed frequency.

[0090] In the second embodiment, the output timing of the digital outputsignal is changed at random to convert the output timing itself and thefrequency of the digital output signal. Therefore, the simultaneousswitching can be more effectively prevented and the amplification of theEMI noise can be reduced.

[0091] Further, in the second embodiment, the output timings of thedigital output signals that are outputted from the signal convertingpart 42 and the amounts of delay of the outputted digital output signalsare changed. Therefore, even when the output timing of the digitaloutput signal from one signal converting part accidentally overlaps theoutput timing from another signal converting part by the random enablesignal, the amount of delay by the delay circuit is changed for each ofthe output timings of the digital output signals. Thus, the changepoints of the digital output signals do not coincide. Accordingly, thegeneration and amplification of the EMI due to the simultaneousswitching of the digital output signals can be more effectivelyprevented or reduced.

[0092] In the above plural embodiments, examples that the presentinvention is applied to the flat bed type image reading apparatus aredescribed. However, the present invention is not limited to the flat bedtype.

1. An image reading apparatus comprising: an image pick-up unit whichconverts inputted light to an analog electric signal and outputs theanalog electric signal; an A/D converting part which converts the analogelectric signal outputted from the image pick-up unit to a digitalelectric signal; an output signal generating unit disposed in an outputside of the A/D converting part, which generates a plurality of digitaloutput signals corresponding to the number of output bits on the basisof the digital electric signal and outputs the digital output signals; aplurality of output wiring parts provided in the output signalgenerating unit correspondingly to the number of the output bits; aclock signal supply unit which supplies clock signals for specifying theoutput timings of the plural digital output signals outputted from theoutput signal generating unit; and an output timing changing unitdisposed in an output side of the output signal generating unit tochange the output timings of the plural digital signals for each of thedigital output signals.
 2. An image reading apparatus according to claim1, characterized in that the output timing changing unit shifts theoutput timing in view of time for each digital output signal forming theplural digital output signals.
 3. An image reading apparatus accordingto claim 2, characterized in that the output timing changing unitincludes a delay circuit part provided in each of the output wiringparts to delay the output timing in view of time for each digital outputsignal.
 4. An image reading apparatus according to claim 3,characterized in that the delay circuit part is set so that an amount ofdelay in time of the digital output signal is different for each delaycircuit part.
 5. An image reading apparatus according to claim 1,characterized in that the output timing changing unit changes afrequency for each digital output signal forming the plural digitaloutput signals.
 6. An image reading apparatus according to claim 5,characterized in that the output timing changing unit includes aplurality of delay circuit parts respectively disposed in the outputwiring parts and a selector for selecting one delay circuit part fromthe plural delay circuit parts.
 7. An image reading apparatuscomprising: an image pick-up unit which converts inputted light to ananalog electric signal and outputs the analog electric signal, a clocksignal generating unit which generates a clock signal for controlling anoperating timing of the image pick-up unit; a control signal generatingunit which generates a plurality of control signals for controlling theoutput tuning of the electric signal synchronously with the clocksignal; and a cross-point adjusting unit which adjusts an amount of timedelay of the plural control signals for each of the control signals andadjusts voltages at cross-points of the plural control signals tospecific voltage characteristic of the image pick-up unit.
 8. An imagereading apparatus according to claim 7, further comprising a recordingunit capable of recording the amounts of time delay of the pluralcontrol signals.
 9. An image reading apparatus according to claim 7,characterized in that the cross-point adjusting unit includes aplurality of delay circuit parts for varying the amount of delay foreach control signal and a selector for selecting a specific delaycircuit part from among the plural delay circuit parts.
 10. An imagereading apparatus according to claim 9, characterized in that theselector selects the specific delay circuit part on the basis of theamount of delay recorded in the recording unit.